1. Field of the Invention
The present invention relates to a semiconductor circuit using a semiconductor element.
2. Description of the Related Art
As one of techniques of a semiconductor circuit, a technique of a switched capacitor circuit has been known in which a switching element (hereinafter also referred to as a switch) is combined with a capacitor and the switching element controls charge and discharge of the capacitor. Since temperature dependence of the electric characteristics of such a switched capacitor circuit is very small, the switched capacitor circuit can be replaced with a resistor in a semiconductor circuit to fabricate a semiconductor circuit having small temperature dependence.
In addition, a technique of using a combination of a switched capacitor circuit and an operational amplifier circuit has been known. When such a semiconductor circuit including a combination of a switched capacitor circuit and an operational amplifier circuit is operated with the use of a clock signal, the semiconductor circuit samples a continuous time signal, which is input to the semiconductor circuit, converts the continuous time signal into a discrete time signal, and outputs the discrete time signal. Depending on the connection method and the operation method, a switched capacitor circuit and an operational amplifier circuit can constitute a circuit such as a filter circuit, an amplifier circuit, an integrating circuit, and a differentiating circuit.
For example, an amplifier (amp) including a combination of these is called a switched capacitor amplifier circuit (see Non-Patent Document 1).
FIG. 11 shows an example of a structure of a switched capacitor amplifier circuit described in Non-Patent Document 1. The switched capacitor amplifier circuit includes three switches (a switch SW1, a switch SW2, and a switch SW3), two capacitors (a capacitor C1 and a capacitor C2), and one operational amplifier circuit. An input signal IN is input to an input terminal of the switched capacitor amplifier circuit. An output signal OUT is output to an output terminal. Here, the voltage of the input signal IN is an input voltage Vin and the voltage of the output signal OUT is an output voltage Vout. The same clock signals S1 are input to the switch SW1 and the switch SW2, and a clock signal S2 having a phase opposite to that of the clock signal S1 is input to the switch SW3. Here, a ground voltage is Vref. A node between the switch SW1 and the capacitor C1 is called a node (A), and a node connected to a minus terminal of the operational amplifier circuit is called a node (B).
There are two periods in the operation of the switched capacitor amplifier circuit, that is, a sampling period during which the input voltage Vin is sampled and a hold period during which the sampled input voltage Vin is amplified and output as the output voltage Vout. As an example, operation of the switched capacitor amplifier circuit shown in FIG. 11 in each period will be described below.
First, in the sampling period, the clock signals S1 and the clock signal S2 are input to turn on the switch SW1 and the switch SW2 and turn off the switch SW3. At this time, when the capacitance of the capacitor C1 is C1, the capacitance of the capacitor C2 is C2, a charge accumulated in an electrode of the capacitor C1 on the node (B) side is Q1, and a charge accumulated in an electrode of the capacitor C2 on the node (B) side is Q2, Q1 and Q2 are expressed by a formula 1.Q1=C1×(Vref−Vin)Q2=C2×(Vref−Vref)=0  [Formula 1]
Next, in the hold period, the clock signals S1 and the clock signal S2 are input to turn off the switch SW1 and the switch SW2 and to turn on the switch SW3. At this time, the potential of the node (B) does not change because the node (B) is virtually grounded by the operational amplifier circuit. Therefore, when a charge accumulated in an electrode of the capacitor C1 on the node (B) side at this time is Q1′ and a charge accumulated in an electrode of the capacitor C2 on the node (B) side at this time is Q2′, Q1′ and Q2′ are expressed by a formula 2.Q1′=C1×(Vref−Vref)=0Q2′=C2×(Vref−Vout)  [Formula 2]
Here, the output voltage Vout is expressed by a formula 3 when it is calculated on the assumption that the total amount of charges accumulated in the capacitors in the sampling period is equal to that in the hold period.
                    Vout        =                                                            C                ⁢                                                                  ⁢                1                                            C                ⁢                                                                  ⁢                2                                      ⁢                          (                              Vin                -                Vref                            )                                +          Vref                                    [                  Formula          ⁢                                          ⁢          3                ]            
As described above, in the switched capacitor amplifier circuit, the input voltage Vin obtained in the sampling period can be amplified depending on the capacitance ratio between the capacitor C1 and the capacitor C2 and can be output in the hold period.